The present invention relates to semiconductor devices and, more particularly, to an MOS-gated power device having a doped polysilicon body and to a process for forming the device
FIG. 1 schematically depicts the cross-section of a trench MOS-gated device 100 of the prior art formed on an upper layer 101a of an N+substrate 101. Device 100 includes a trench 102 whose sidewalls 103 and floor 104 are lined with a gate dielectric such as silicon dioxide. Trench 102 is filled with a conductive material 105 such as doped polysilicon, which serves as an electrode for gate region 106.
Upper layer 101a of substrate 101 further includes P-well regions 107 overlying an N-drain zone 108. Disposed within P-well regions 107 at an upper surface 109 of upper layer 101a are heavily doped P+body regions 110 and heavily doped N+source regions 111. An interlevel dielectric layer 112 is formed over gate region 106 and source regions 111. Contact openings 113 enable metal layer 114 to contact body regions 110 and source regions 111. A drain metal layer 115 is applied to the rear surface of N+substrate 101.
FIG. 2 is a schematic cross-sectional view of a vertical planar MOSFET device 200 of the prior art formed on an upper layer 101a of an N+substrate 101. Device 200 includes a planar gate region 201 comprising a gate dielectric layer 202, silicon oxide, for example, and a conductive layer 203, doped polysilicon, for example, that serves as a gate electrode.
Device 200 resembles device 100 in that upper layer 101a further includes P-well regions 107 overlying an N-drain zone 108, and heavily doped P+body regions 110 and heavily doped N+source regions 111 disposed within P-well regions 107 at upper surface 109 of upper layer 101a. An interlevel dielectric layer 112 is formed over gate region 201 and source regions 111, and contact openings 113 enable metal layer 114 to contact body and source regions 110 and 111, respectively. A drain metal layer 115 is applied to the rear surface of N+substrate 101. The body and source regions of devices currently in common use, for example, structures 100 and 200 depicted in FIGS. 1 and 2, respectively, are typically formed by successive implantation and diffusion of dopants of opposite conduction type into a semiconductor substrate, a procedure that requires the use of two photoresist masks, one for the source, the other for the body. Lateral diffusion of dopants, high energy implantation scatter during body formation, and allowance for possible misalignment are factors that adversely affect efforts to reduce the size of the device. There is a need for power devices of reduced size relative to those in current use the present invention meets this need.
The present invention is directed to an improved MOS-gated power device on a substrate having an upper layer of doped monocrystalline silicon of a first conduction type that includes a doped well region of a second conduction type. The substrate further comprises at least one heavily doped source region of the first conduction type disposed in the well region at an upper surface of the upper layer, a gate region comprising a conductive material electrically insulated from the source region by a dielectric material, a patterned interlevel dielectric layer on the upper surface overlying the gate and source regions, and a heavily doped drain region of the first conduction type. The improvement comprises: body regions comprising heavily doped polysilicon of the second conduction type disposed in the well region at the upper surface of the monocrystalline silicon substrate.
The invention is further directed to a process for forming an MOS-gated power device that comprises: providing a substrate having an upper layer of doped monocrystalline silicon of a first conduction type that includes a doped well region of a second conduction type. The substrate further comprises a heavily doped source regions of the first conduction type disposed in the well region at an upper surface of the upper layer, a gate region comprising a conductive material electrically insulated from the source region by a dielectric material, heavily doped drain region of the first conduction type, a patterned interlevel dielectric layer on the upper surface overlying the gate and source regions.
The process further comprises: forming a body mask on the substrate, and selectively removing portions of the source region and underlying well region remotely disposed from the gate region, thereby forming at least one body hollow in the substrate; removing the body mask, and forming a blanket layer of heavily doped polysilicon of the second conduction type that overlies the substrate and interlevel dielectric layer and fills the body hollow; selectively removing portions of the polysilicon blanket layer from the source region and interlevel dielectric layer, leaving heavily doped polysilicon filling the body hollow and thereby forming a body region; depositing over the upper surface and interlevel dielectric layer a source metal layer in electrical contact with the source and body regions; and forming a drain metal layer in contact with the drain region in the substrate.